Keynotes & Invited talks

Keynote Speakers

• Prof. Shinji Kaneko, Hiroshima University, Japan
  Topic: Town & Gown Initiative as a new strategy for establishing smart innovation ecosystem in university town in Japan.
  Click here for the abstract.

  Hiroshima University has launched the Town & Gown Initiative with the City of Higashi-Hiroshima. This is a model foruniversity contribution to create a new sustainable future society whilesolving local problems and challenges. Over the past three years, HiroshimaUniversity have been working on activities such as digital transformation andgreen transformation and have begun to launch a demonstration project oncampus. Many companies have begun to participate. And we have decided to builda new building on campus to serve as an incubation center to convert theuniversity's research findings and technological development to socialimplementation. Furthermore, the Japan-U.S. semiconductor collaboration thatwas agreed at the Hiroshima G7 Summit should have a great impact on the region,and we are now in a situation where we can expect great synergy with this smartcity project of Hiroshima University. After this, we would like to expand theproject to fields other than semiconductors, such as genome editing, drugdiscovery, energy, and robotics, and turn the area around the university intoan innovation ecosystem.

• Prof. Hafizur Rahaman, IIEST Shibpur, India
  Topic: Memristors Based In-memory Computing for Edge Computing Applications
  Click here for the abstract.

  The data processing and computation task has significantly shifted from the cloud towards the edge devices by leveraging the properties of the recent development in sensors and edge device hardware. The current requirement for edge devices to perform intelligent computation with real-time processing has created a need to improve edge applications' hardware performance. Nowadays, sensors can meet the demand for high-end hardware, so data processing has shifted to near-sensor-based processing. The artificial intelligence chip market has shown rapid growth for edge devices by utilizing machine learning networks. The information from the data is converted from analogue to digital domain by sensors, filtered and processed for realizing various neural networks. However, the significant problem is device scaling to sub-micron ranges. This problem is addressed, and many emerging technologies like memristor have shown improved performance at submicron ranges. This emerging technology can also process analogue data by mapping neural networks on the memristive array-based computation designs. The growth of edge devices has been mainly driven by high data computation and low-power chip designs over the last few years. And the constraint of device scaling has shifted the data computation towards neural networks. Various technologies have evolved during the past year for edge devices to perform computation far from CMOS technology, which follows Moore's law. The hardware technologies which drive this development are Logic Synthesis and mapping, Memory design, non-volatile memories, flash memory, area-latency scaling, and 3D devices. The benchmark criterion to move beyond Moore's law for coming years are (1) a 15% improvement in the operating frequency concerning supply voltage, (2) a reduction in energy consumption by 35% per switching, (3) reducing the on-chip area footprint by 45%, and (4) reducing the die cost by 25%. For edge AI applications, the memory and the logic technologies shape the hardware development for data processing and computation. Memristive devices are evolving as non-volatile memories, with various features suitable for growth in this field. There are many non-volatile alternatives of memristor devices, like PCM- phase change memory, ReRAM-resistive random access memory, and MRAM-magnetic RAM, suitable for designing neural networks for edge device computations.

Invited Speakers

• Dr. Mehdi Saligane, University of Michigan, USA
  Topic: OpenFASOC: An Open platform towards analog and mixed-signal analog automation and democratizing chip design
  Click here for the abstract.

  The democratization of chip design has revolutionized the field of analog and mixed-signal design by incorporating software practices into the development process. OpenFASOC, an open-source framework, has emerged as a suite of tools that automates the analog and mixed-signal design process. By leveraging a combination of design methodologies and tools, OpenFASOC strikes a balance between complexity and design performance. The framework employs a procedure-based approach with a cell-based flow using highly automated digital APR tools, as well as a programmatic layout approach that offers greater layout configurability. Circuit generators within OpenFASOC, such as power management sensing and interface circuits, are programmed to access a library of customized analog "Auxiliary Cells" and seamlessly integrate them with digital components using a layout template. These procedure-based generators combine open-source tools with custom Python scripts to enable automated mixed-signal design. Furthermore, OpenFASOC addresses the custom design time of auxiliary cells by currently developing support for programmatic layout, utilizing GDSfactory-based Python scripts to codify layout into component classes. This approach facilitates the quick creation of layouts from Python functions, enabling reuse across designs with varying sizes. By combining these design methodologies, OpenFASOC empowers the generation of tape-out ready circuits from high-level specifications. The democratization of chip design, facilitated by OpenFASOC, has not only accelerated the design process but has also fostered innovation and expanded possibilities within the field.

• Dr. Manodipan Sahoo, IIT (ISM) Dhanbad, India
  Topic: Design of low-power and high-performance SRAM using Electrostatically doped TMD TFET for the 10 nm node
  Click here for the abstract.

  The projected nodes of International Roadmap for Devices and Systems (IRDS) can't simply be achieved by reducing the feature size. To control the entire channel, the gate capacitance, which is based on the gate size and the gate dielectric characteristics, must be sufficiently large. The difficulty of maintaining enough gate capacitance as devices get smaller is one of several challenging issues. So, the thrust to enhance the gate capacitance has driven numerous improvements to transistor design as well as an investigation into alternate architectures and channel materials. Architecture such as FinFETs solve the issue. However, even more extreme remedies are required, as the channel length continues to decrease. By applying electric fields in all directions, nanowires, nanosheets and, other gate-all-around (GAA) transistor designs improve channel control. However, in the long run, it is anticipated that GAA performance will deteriorate at ultimate channel thickness scaling of Si due to increased electron-phonon and surface-roughness scattering brought on by a higher surface-to-volume ratio. An alternative option is 2D material-based channel because when the channel is scaled down, the thickness of the channel should also be as thin as possible to enable a strong gate control on the channel. Thus, researchers have investigated monolayer 2D materials-based FET to get to its ultimate scaling limit along with applicability for high performance and low power applications as per IRDS projections. In this talk, a comparison of the Electrostatically Doped Tunnel Field-Effect Transistor (EDTFET) with monolayer 2D Transition Metal Dichalcogenide (TMD) as channel material and Si MOSFET-based Static Random Access Memory (SRAM) has been carried out at the circuit level using a Verilog-A interface. A 6T SRAM has been implemented in Cadence Virtuoso for this comparison purpose. It has been observed that the EDTFET-based SRAM demonstrates superior performance in terms of HOLD, WRITE, and READ noise margins and delay, while maintaining power dissipation at a comparable level. The HOLD, WRITE and, READ noise margins of the EDTFET are observed to be 0.2313 V, 0.06 V, and 0.2824 V, which are 33.93 %, 20 %, and 31.96 % higher than the HOLD, WRITE, and READ noise margins of the Si MOSFET-based SRAM, respectively. The delay achieved by our proposed EDTFET-based SRAM is ~4 decades lower than that of the Si MOSFET-based SRAM.

• Dr. Sayan Kanungo, BITS Pilani (Hyderabad), India
  Topic: Integration of the Two-dimensional Materials in Nano-scale MOSFET Design- Prospects and Challenges
  Click here for the abstract.

  The ever increasing demand for high performance and miniaturization has pushed the bulk-Complementary Metal Oxide Semiconductor (CMOS) technology to its limit. The short channel effects are gradually becoming the most severe bottleneck for sustaining the continuous downscaling of conventional Metal Oxide Semiconductor Feld Effect Transistors (MOSFETs), leading to the emergence of post-CMOS devices like Ultra-Thin Body Field Effect Transistor (UTB-FET) and Fin Field Effect Transistor (Fin-FET). The further downscaling in UTB-FET/ Fin-FET imposes a severe design challenge for gate length reduction while retaining channel electrostatic integrity, necessitating UTB/fin width specifications in the range of a few nanometres for reducing the geometric scaling length. Unfortunately, such technological demands are primarily bottlenecked by conventional Silicon (Si) technology. The aggressive downscaling of bulk Si-based fin/sheet dimension results in strong size-quantization effects and charge carrier mobility degradations. In this context, an ever-increasing research effort has been observed to replace the Si in UTB/fin with two-dimensional (2D) semiconductors of one or few atomic layer thicknesses. Such 2D materials-based technology holds immense prospects for complementing or replacing present Si-based transistor design for high-performance and low-power applications. However, despite its inherent potential, the proposed 2D material-based technology has unique design challenges where the most severe bottlenecks are presented in terms of reliable, large-area growth of 2D materials with high yield and compatibility of 2D materials with the material systems in conventional Silicon process flow. Motivated by this paradigm, the proposed talk will primarily be focused on reviewing the development of 2D material for nano-scale transistor design, emphasizing the design and fabrication challenges and their potential technological solutions. In this context, the state-of-the-art in 2D material research, as well as 2D-FET design will be highlighted with their future prospect. Finally, a bird-eye-view of 2D-FET technology for emerging electronic applications will be briefly presented.

• Dr. Koh Joguchi, Shinshu University, Japan
  Topic: Smart Sensing Circuit Design in IoT Era
  Click here for the abstract.

  This talk presents three design examples of smart sensing circuit designs for IoT era. A wearable perspiration sensor has been designed with custom chip on a flexible board with micro-blower driver and PDMS micro flow-path. Also, a custom designed analog frontend circuit has been designed for FBG sensor that can be weaved into clothes. A smart ultrasonic water flow-meter can measure flow-rate in real-time correctly, that enables smart meter services. In IoT era, smart Sensors are typically connected to the internet through digital inputs and outputs and measure and record specific parameters. These parameters include many physical and environmental conditions, such as temperature, humidity, pressure, sound, light, wind speed and direction, vibration, radiation, electrical and magnetic properties, and the presence or location of objects. These sensors collect data in real-time and transmit the data over a network. In this way, systems can monitor, analyze, and control these parameters from a remote location. Some IoT Smart Sensors utilize "edge computing," where they process data locally and send only necessary information to the cloud. This significantly reduces communication costs and latency and enhances security and privacy. These sensors are used in applications such as smart homes, industrial automation, environmental monitoring, agriculture, energy management, healthcare, military applications, and many other areas. Could servers or data center require machine power or calculation power to manage and compute these data. On the other hand, for smart sensors, it is not essential. But cost is most important factor because number of sensors is needed and these should be low cost. Most smart sensors consist of analog circuit. In analog circuit, large gate length is necessary to mitigate short channel effect. Some smart devices include digital circuit for edge computing, but it is not large scale. Therefore, for these devices, the legacy process is suitable. In this talk, three design examples are presented. The first is perspiration monitoring system for daily healthcare applications [1-5]. The second design is a FBG vital sign sensor for medical application [6-8]. The third example is a smart ultrasonic water flow meter design [9,10]. REFERENCES [1] Y. Mitani, K. Miyaji, S. Kaneko, T. Uekura, H. Momose, and K. Johguchi, "A compact sweat monitoring system with CMOS capacitive humidity sensor for wearable health-care application", SSDM2017, p. 261, 2017. [2] Y. Mitani, K. Miyaji, S. Kaneko, T. Uekura, H. Momose, and K. Johguchi, "A compact perspiration meter system with capacitive humidity sensor for wearable health-care applications", Japanese Journal of Applied Physics 57, 04FF10, 2018. [3] T. Sakata, Y. Mitani, K. Miyaji, S. Kaneko, Y. Uekura, H. Taki, H. Momose, and K. Johguchi, "A CMOS integrated sweat monitoring system for medical applications", Proc. 2nd International Symposium on Devices, Circuits and Systems (ISDCS2019), 2019. [4] A. Yamamoto, Y. Kaga, T. Aso, S. Kuroki, H. Momose, and K. Johguchi, "A high-precision wearable perspiration monitor with 0.18 um BCD process and PDMS micro air-flow path", Ext. Abst. 2022 International Solid State Devices and Materials, pp. 727-728, 2022. [5] A. Yamamoto, Y. Kaga, T. Aso, S. Kuroki, H. Momose, and K. Johguchi, "Flexible and compact persipiration monitoring system with 0.18 um BCD process and PDMS micro air-flow path" Japanese Journal of Applied. Physics, 62, SC1078, 2023. [6] H. Ishizawa, Y. Haseda and K. Johguchi, "Wearable vital sign sensing technology based on FBG sensor system," Ext. Abst. of SSDM2019, pp. 551-552, 2019. [7] S. Chino, H. Ishizawa, S. Koyama, K. Fujimoto, S. Kurasawa and K. Katayama, "Study on pulse wave pattern for blood pressure prediction using FBG sensor, " Transactions of the Society of Instrument and Control Engineers, Vol. 56, No. 4, pp. 189-197, 2020. [8] Y. Haseda, M. Masuko, K. Fujimoto, S. Koyama, and H. Ishizawa, "Verification of non-invasive blood glucose measurement based on pulse wave by FBG sensor," Transactions of the Society of Instrument and Control Engineers, Vol. 57, No.7, pp. 314-323, 2021. [9] Y. Kaga and K. Johguchi, "A smart ultra-sonic water-flow meter with 180-nm CMOS technology," Ext. Abst. 2020 International Solid State Devices and Materials, 2020. [10] Y. Kaga and K. Johguchi, "A 180 nm CMOS smart ultrasonic water flow meter circuit for IoT smart society," Japanese Journal of Applied. Physics, 60, SBBL05, 2021.

• Dr. Tapas Kumar Maiti, DA-IICT, India
  Topic: Robot Movement Visualization Based on Component-Oriented Simulation
  Click here for the abstract.

  Robot-component oriented modeling, simulation, and visualization of its movements are performed using circuit and robot simulators. A co-simulation framework is developed to combine the circuit simulator and robot simulator, which fed the data from circuit simulator to robot simulator. The component-oriented models are developed on the basis of transformation of information entities such as position, force, or torque by employing the power-conservation conditions. We visualize the robot-arm movements with robotics simulator CoppeliaSim. Furthermore we discussed the development of efficient robot with component-oriented optimization by picking proper motors, and robotic mechanical properties such as length, height, weight, etc.

• Dr. Nezam Rohbani, Institute for Research in Fundamental Sciences, Teheran
  Topic: PF-DRAM: A Precharge-Free DRAM Structure
  Click here for the abstract.

  DRAM (Dynamic Random Access Memory) is a type of computer memory that is widely used in today's electronic devices. It is an essential component in modern-day computing, and its performance can significantly affect the overall performance of a computer system. While DRAM capacity and bandwidth have increased significantly due to advances in technology and standards, its latency and energy per access have remained almost constant in recent generations. One of the main challenges in DRAM design is power consumption, as the majority of DRAM power is dissipated by Read, Write, and Refresh operations, all initiated by a Precharge phase. This Precharge phase not only consumes a large amount of energy, but it also increases the delay of closing a row in a memory block to open another one. Recent workloads, especially in multi-core systems, have shown a reduction in row-hit rate, resulting in an increase in precharge rate, which exacerbates DRAM power dissipation and access latency. To address this challenge, a novel DRAM structure called Precharge-Free DRAM (PF-DRAM) has been proposed in recent research. PF-DRAM eliminates the Precharge phase of DRAM and uses the charge on bitlines from the previous Activation phase as the starting point for the next Activation. The difference between PF-DRAM and conventional DRAM structures is limited to precharge and equalizer circuitry and simple modifications in the sense amplifier, which are all limited to the subarray level. The benefits of PF-DRAM are substantial. First, it significantly reduces power consumption in DRAM. Experimental results on an 8GB memory system running SPEC CPU2017 and PARSEC 2.1 workloads show an average of 35.3 percent memory power consumption reduction (up to 54.2 percent) achieved by the system using PF-DRAM with respect to the system using conventional DRAM. Moreover, PF-DRAM also improves overall system performance. The same experimental results show an overall performance improvement of 8.6 percent (up to 24.3 percent) achieved by the system using PF-DRAM compared to the system using conventional DRAM. This improvement in performance is due to the elimination of the precharge phase and the faster access time provided by PF-DRAM. Furthermore, PF-DRAM is compatible with mainstream JEDEC memory standards such as DDRx and HBM, with minimal modifications required in the memory controller. Additionally, most of the previously proposed power/energy reduction techniques in DRAM can still be applied to PF-DRAM for further improvement.

• Prof. Hitoshi Wakabayashi, Tokyo Institute of Technology, Japan
  
• Ms. Kumari Neeraj Kaushal, Indian Institute of Technology Gandhinagar, India
  Topic: Advancing High Voltage MOS Transistor Compact Models Through Physical Augmentation: Techniques and Applications
  Click here for the abstract.

  High Voltage MOS (HVMOS) transistors are extensively used in Power Management ICs (PMICs), automotive electronics, consumer electronics, RF communication systems and space applications. The accurate high voltage transistor compact models are an essential tool for designing and optimizing HVMOS circuits for such applications. However, the complex device structure and associated anomalous device effects pose several challenges to the accurate modeling of HVMOS transistors. Moreover, the existing high voltage transistor compact models have limitations in accurately capturing the anomalous device effects specific to HVMOS transistors. In this talk, we will present different augmentations we have done to enhance the accuracy and applicability of the industry-standard HiSIM-HV model. We have used physics-based models to capture anomalous device effects such as the boost in conductivity because of Channel Doping Gradient (CDG), the internal drain voltage (VK) modulation and its effect on substrate current behavior. We have developed a new physics-based parameter extraction methodology (based on the HiSIM-HV) to capture the Channel Doping Gradient effect on HVMOS transistors. The VK plays a significant role in determining the impact ionization, substrate current and capacitance-voltage characteristics of HVMOS transistors. We have proposed an innovative VK model that accurately captures the VK modulation with gate and drain voltages, while capturing the physics of space charge modulation. The VK model is then used to develop scalable, robust substrate current model. The utility of the VK model in determining the LDMOS capacitance behavior is also analyzed. Additionally, we have also modeled the behavior of HVMOS transistors in cryogenic operating conditions. We have shown that the carrier freeze-out (Incomplete Ionization) and field assisted ionization in the drift region are critical to high voltage MOS transistor behavior at extremely low operating temperatures. The HiSIM-HV model is augmented with new model equations to extend the model validity in 77-300K temperature range. The fully developed model is validated using experimental data from fabricated N- and P-HVMOS transistors. The to-be-discussed models and techniques will provide valuable insights into the design and performance of the HVMOS transistors under different operating conditions and will pave the way for development of more efficient and reliable high voltage and high-power systems.

• Dr. Toshitsugu Sakamoto, Co-founder, NanoBridge Semiconductor, Inc. Japan.
  Topic: Low power programmable logic using NanoBridge technology
  Click here for the abstract.

  We have developed NanoBridge based field programmable gate array (NB-FPGA). The NanoBridge with non-volatility replaces both configuration RAM and pass transistor in FPGA. NB-FPGA provides high energy efficiency for AI application in IoT devices. Non-volatility provides in the intermittent operation and the reduction of standby power in the sleep mode of the system. The NanoBridge is composed of the polymer solid electrolyte (PSE) sandwiched between Ru and Cu electrodes. The NanoBridge is implemented in the interconnects of LSI. When a positive voltage is applied to the Cu, Cu is ionized and precipitated at the Ru electrode, and then a thin Cu metal bridge is formed between the two electrodes. And the conductance of the switch changes to high (or on state). This is the set operation. When a negative voltage is applied, the switch turns off. A 171k-LUT NB-FPGA is fabricated by using the 28nm CMOS technology. The NanoBridge is implemented between metal 4 and metal 5 in 9-layer Cu interconnects and CMOS. The total number of LUT is 171k, which satisfies the requirement of CNN execution. NB-FPGA includes 3.2 Mb block RAMs (BRAM), 200-MHz phase locked loops, 648 digital signal processors (DSP), single-precision floating point units. The fabricated chip is evaluated to clarify the layout area reduction and performance gain.

• Prof. Rolf Drechsler, University of Bremen
  Topic: Towards Polynomial Formal Verification of AI-Generated Arithmetic Circuits
  Click here for the abstract.

  The popularity of Artiicial Intelligence (AI) is growing in many domains. The designers have started to use AI in Electronic Design Automation (EDA) for the generation of highly optimized digital designs, particularly arithmetic circuits. The arithmetic blocks generated by deep and reincement learning usually outperform the generic architectures in terms of design characteristics such as area, delay, power, and the number of wiring tracks. As a result, it is expected that AI-generated arithmetic circuits will soon occupy an important place in many applications thanks to their highly efficient architectures. A crucial task after the design of an arithmetic circuit, including AI-generated circuits, is formal veriication. Formal methods can detect faulty designs before fabrication and prevent fancial loss and disastrous consequences. Despite the huge progress of formal methods in veriying a wide variety of designs, their time and space complexity is not fully investigated, particularly for the AI-generated arithmetic circuits. Here, we calculate the time complexity of formal veriication based on Binary Decision Diagrams (BDDs) when it comes to proving the correctness of general prefx adders. We prove that the formal veriication of a prefx adder is possible in polynomial time independent of the prefx tree structure. Our proof is valid for both regular prefx adders generated by known algorithms and irregular prefx adders generated by AI.